Semiconductors, Micro/Nanofabrication, and VLSI¶

Audience¶

Learners seeking the full chain from devices and fabrication to digital IC physical implementation

Final outcome¶

Complete a chip project with device assumptions, timing/power constraints, verification, and reviewable layout or process plan.

Stages¶

Device physics¶

Selection rule: Complete all 2 required courses and choose 1 of 3 elective options.

• Quantum Physics I — Elective option; MIT; Alternative; A
• Microelectronics — Required; Cornell University; Mainline; S
• Microelectronic Devices and Circuits — Elective option; MIT; Alternative; A
• Physics of Semiconductors and Nanostructures — Required; Cornell University; Mainline; A
• Introduction to Nanoelectronics — Elective option; MIT; Alternative; A

Stage exit criterion: Derive device I–V/C–V behavior from band and transport assumptions and extract compact-model parameters from public or simulated data; normalized RMSE over a held-out bias interval must not exceed 10%.

Fabrication¶

Selection rule: Complete all 2 required courses and choose 1 of 2 elective options.

• Micro/Nano Processing Technology — Required; MIT; Mainline; S
• Micro and Nanofabrication (MEMS) — Elective option; EPFL; Alternative; A
• Basic Overview of Semiconductor Device Processing and IC Fabrication — Elective option; IIT Kanpur / NPTEL; Supplement; A
• Design and Fabrication of Microelectromechanical Devices — Required; MIT; Mainline; A

Stage exit criterion: Submit mask layers, cross sections, and a stepwise process flow with tolerances for at least three critical dimensions; use design-rule checks and an FMEA to explain dominant failure mechanisms and quantify one yield-sensitivity result.

VLSI design¶

Selection rule: Complete all 1 required course and choose 1 of 3 elective options.

• Digital Design and Integrated Circuits — Elective option; University of California, Berkeley; Alternative; B
• Complex Digital Systems — Elective option; MIT; Supplement; B
• Analysis and Design of Digital Integrated Circuits — Required; MIT; Mainline; A
• VLSI Systems — Elective option; Cornell University; Supplement; A

Stage exit criterion: Complete the specification, RTL, verification, and implementation report for a synthesizable digital block; regression must have zero mismatches, timing must close under target constraints, and the report must show area, a power proxy, and at least one design-space tradeoff.

Execution rules¶

• Follow each stage's selection rule: complete every required course and the stated number of electives; when complete path options are provided, choose one and finish every course in its listed order; use optional supplements only to close a specific gap.
• Produce at least one reproducible artifact per stage and include failed attempts in the retrospective.
• Work involving mains voltage, high voltage, RF exposure, lasers, chemicals, or fabrication equipment requires local-law compliance and qualified supervision.