Analog, Mixed-Signal, and Integrated Circuits¶

Audience¶

Learners progressing from circuits and devices to transistor-level design, simulation, and layout

Final outcome¶

Complete an analog or mixed-signal design with specifications, corner simulation, noise/power tradeoffs, and layout checks.

Stages¶

Circuits and devices¶

Selection rule: Complete all 3 required courses and choose 1 of 2 elective options.

• Circuits and Electronics — Required; MIT; Mainline; S
• Microelectronics — Required; Cornell University; Mainline; S
• Microelectronic Devices and Circuits — Elective option; MIT; Alternative; A
• Microelectronic Devices and Circuits — Elective option; University of California, Berkeley; Alternative; A
• Physics of Semiconductors and Nanostructures — Required; Cornell University; Mainline; A

Stage exit criterion: Extract MOS-device parameters from public or simulated I–V/C–V curves and use the same model to predict a bias circuit's DC, AC, and transient responses; normalized RMSE on held-out data must stay below 10%.

Analog design¶

Selection rule: Complete all 1 required course and choose 2 of 3 elective options. The other course is an optional supplement and does not count toward the elective requirement.

• Introductory Analog Electronics Laboratory — Required; MIT; Mainline; S
• Solid-State Circuits — Elective option; MIT; Supplement; B
• Analog Circuits — Elective option; IIT Bombay / NPTEL; Alternative; A
• Integrated Circuits, MOSFETs, OP-Amps and Their Applications — Elective option; Indian Institute of Science / NPTEL; Alternative; A
• Analog IC Design — Optional supplement; IIT Madras / NPTEL; Mainline; A; Audit review

Stage exit criterion: Design an op-amp or low-noise front end and verify gain, bandwidth, phase margin, noise, slew rate, and power specifications individually; all PVT and load corners must pass, or any miss must be captured as a reproducible tradeoff.

Integrated implementation¶

Selection rule: Complete all 2 required courses; use the other 1 option only to close a specific gap.

• Analysis and Design of Digital Integrated Circuits — Required; MIT; Mainline; A
• VLSI Systems — Optional supplement; Cornell University; Supplement; A
• Micro/Nano Processing Technology — Required; MIT; Mainline; S

Stage exit criterion: Submit a layout and signoff package with explicit process assumptions, zero DRC and LVS errors, and a pre- versus post-layout comparison of key metrics; parasitic-driven changes must be quantified and every specification miss must have a layout-level remedy.

Execution rules¶

• Follow each stage's selection rule: complete every required course and the stated number of electives; when complete path options are provided, choose one and finish every course in its listed order; use optional supplements only to close a specific gap.
• Produce at least one reproducible artifact per stage and include failed attempts in the retrospective.
• Work involving mains voltage, high voltage, RF exposure, lasers, chemicals, or fabrication equipment requires local-law compliance and qualified supervision.