Digital Design and Integrated Circuits¶

Course Overview¶

• Institution: University of California, Berkeley
• Course code: EECS 151
• Track: Digital VLSI and Chip Design
• Tier: B
• Role: Alternative
• Level: Not standardized by provider (use prerequisites)
• Last reviewed: 2026-07-28

University of California, Berkeley's Digital Design and Integrated Circuits provides a current curriculum identity and scope for digital IC design, but the public catalog is not an independently executable teaching spine, its archives require CalNet, and industrial EDA labs are restricted.

Why choose this course

Alternative course. Useful for specific topics and best paired with a more complete mainline resource. Review note: A curriculum identity / B public completion

Before you start

• Recommended foundation: Microelectronics
• Recommended foundation: Digital Logic and Computation Structures

Verifiable learning outcomes

• Explain the core models in Digital VLSI and Chip Design, including their assumptions and limits

Workload and pacing

8 weeks at 6 hours/week. This maintainer planning estimate is derived from course role and the density of public practice and labs; it is not a provider workload promise. Pilot two weeks while logging instruction, practice, lab, and review time, then adjust the remaining plan when actual effort differs by more than 25%.

Safety level

Simulation only. The default practice scope is software, computation, or simulation only; a lab label in the resource inventory does not authorize connecting physical equipment, and any hardware extension requires provider-scope verification and a new risk assessment.

Course Resources¶

Software, hardware, and cost

Software

• Maintainer-suggested open-source/free verification path: Yosys, OpenROAD, OpenSTA, Verilator, GTKWave, and KLayout
• The resource inventory does not list public code coverage; the tools above are only a maintainer-suggested independent check, not a provider requirement

Hardware

• The resource inventory does not list public physical-lab coverage; the maintainer path defaults to computation/simulation. It assumes only a computer with enough memory and storage for synthesis, place-and-route, and regressions; no tape-out is assumed. If the provider lists different equipment or compute requirements, follow its course page

Cost note

The suggested software stack is available open source or free; this is maintainer planning, not a provider requirement. If the provider specifies commercial licenses, cloud compute, storage, or institutional resources, costs vary by plan, region, and institution, so no fixed price is asserted here.

Public resource coverage

Resources and access

“Listed by official page” means the link was discovered on a successfully fetched official source on the verification date; it does not guarantee that every region or account can open the target directly. Access does not grant redistribution rights. Re-check the provider page, target link, and third-party notices before downloading, adapting, or publishing material.

Practice and Verification¶

Practice loop

Digital Design and Integrated Circuits · University of California, Berkeley EECS 151: RTL-to-Layout PPA and Equivalence Audit

This is a maintainer-suggested self-study project for Digital Design and Integrated Circuits · University of California, Berkeley EECS 151, not an official course assignment. Take a compact digital core through a lawfully available synthesis and place-and-route flow for Digital VLSI and Chip Design, auditing functional equivalence, timing, power proxies, and congestion.

Origin: Maintainer-suggested project

Deliverables

• RTL, interface, clock and reset specification, timing constraints, and PPA targets
• Reproducible synthesis, place-and-route, static-timing, and equivalence-check source files and scripts
• Netlists, constraints, raw area, timing, power-proxy, congestion, and DRC summaries
• A report comparing at least three constraint points and reviewing one timing or congestion failure

Verification

• Pass RTL-to-gate equivalence and functional regression with zero failures
• Cover slow and fast corners, minimum and maximum loads, and at least 2 clock targets
• Make a hand logic-depth estimate agree directionally with STA and explain the quantitative gap
• Tighten the clock until first negative slack, locate the path, and quantify the cost of the fix

Reproducibility

• Commit RTL, constraints, flow scripts, configurations, tests, and a README
• Pin the lawfully available PDK or cell-library version, EDA container or tools, and seeds
• Preserve raw logs, netlists, reports, failing-run configurations, and checksums

Safety boundary: Simulation only — Run only lawfully authorized digital EDA flows; do not submit for fabrication, handle restricted PDK data, or bypass licenses.

Risks, gaps, and boundaries

The current catalog confirms the curriculum, but its course archives require CalNet and the industrial EDA laboratories are restricted; this record is not an independently executable public course.

Completion evidence

• Weekly learning log with time, questions, corrected errors, decisions, next steps, and links to that week's reproducible artifacts
• Design-review package with requirements and constraints, trade-offs, editable sources, applicable ERC/DRC/timing/stability checks, exports, and a reproduction test
• Code repository with pinned dependencies and toolchain, a minimal run command, tests or waveform/benchmark checks, expected output, and license notes
• Simulation package with model or netlist, inputs, solver and version, parameter-sweep script, benchmark comparison, expected results, and one rerun command