The Art and Science of PCB Design¶

Course Overview¶

• Institution: MIT
• Course code: IAP PCB 2026
• Track: PCB, EDA, and Hardware Verification
• Tier: S
• Role: Mainline
• Level: Not standardized by provider (use prerequisites)
• Last reviewed: 2026-07-28

MIT's The Art and Science of PCB Design builds a PCB-design spine through eight KiCad and Altium labs plus videos, notes, and code, with fabrication cost and some video access still requiring checks.

Why choose this course

Mainline course. A particularly complete and well-structured option for this track.

Before you start

• Recommended foundation: Circuit Analysis
• Recommended foundation: Electronics Laboratory and Measurement

Verifiable learning outcomes

• Explain the core models in PCB, EDA, and Hardware Verification, including their assumptions and limits
• Solve representative derivations and problems, checking units, limiting cases, or numerical results
• Complete a reproducible experiment or implementation with raw data, parameters, versions, and verification

Workload and pacing

13 weeks at 11 hours/week. This maintainer planning estimate is derived from course role and the density of public practice and labs; it is not a provider workload promise. Pilot two weeks while logging instruction, practice, lab, and review time, then adjust the remaining plan when actual effort differs by more than 25%.

Safety level

Low energy. Keep work isolated, current-limited, and low energy; verify ratings, grounding, short-circuit risk, and emergency shutdown before power-up.

Course Resources¶

Software, hardware, and cost

Software

• Maintainer-suggested open-source/free verification path: KiCad (schematic, PCB, and ngspice), gerbv, and Git
• The resource inventory lists public code coverage; pin interpreter, dependencies, toolchain, datasets, and PDK versions where applicable

Hardware

• The resource inventory lists lab coverage; prefer borrowing or sharing the following equipment: course-specified components, prototype PCB, current-limited supply, digital multimeter, and oscilloscope only after design checks pass. Verify ratings, authorization, and safety conditions only after the provider lab manual explicitly calls for them

Cost note

The suggested software stack is available open source or free; this is not a provider requirement or bill of materials. The actual boards, components, fabrication, and instruments—and their costs—depend on the provider lab manual, region, and local availability; prefer simulation, borrowing, or sharing before purchase.

Public resource coverage

Resources and access

“Listed by official page” means the link was discovered on a successfully fetched official source on the verification date; it does not guarantee that every region or account can open the target directly. Access does not grant redistribution rights. Re-check the provider page, target link, and third-party notices before downloading, adapting, or publishing material.

Practice and Verification¶

Practice loop

The Art and Science of PCB Design · MIT IAP PCB 2026: Manufacturable Low-Voltage Test Board Review

This is a maintainer-suggested self-study project for The Art and Science of PCB Design · MIT IAP PCB 2026, not an official course assignment. Design a passive or small-signal test board at or below 5 V for PCB, EDA, and Hardware Verification, completing rule checks, BOM, manufacturing outputs, testability, and an optional current-limited bring-up plan.

Origin: Maintainer-suggested project

Deliverables

• Requirements, interfaces and ratings, power tree, risks, schematic, and design-review checklist
• PCB sources, footprint or 3D checks, DRC and ERC configuration, and versioned libraries
• Gerber, drill, position, BOM, and other manufacturing outputs with raw check reports
• A testability and bring-up report with test points, expected readings, budget, and failure review

Verification

• Have 0 unexplained ERC or DRC errors and traceable checks for every interface, supply, and component rating
• Cover reversed connector, do-not-populate, short, open, and probe-access boundaries
• Cross-check layers, drills, and connectivity with an independent Gerber viewer and netlist comparison
• Deliberately remove a decoupler or test point or change a footprint and show the review checklist catches the regression

Reproducibility

• Commit schematic, PCB, libraries, BOM, manufacturing, and review sources
• Pin EDA version, design rules, library commit hashes, and generation commands
• Preserve raw ERC, DRC, manufacturing checks, optional bring-up data, and the generated report

Safety boundary: Low energy — If fabricated, limit operation to isolated, current-limited supplies at or below 5 V; verify component and connector ratings, solder and wire with power removed, and current-limit first power-up. No mains, battery packs, high current, or hot loads.

Risks, gaps, and boundaries

The CC BY-SA course includes eight KiCad and Altium laboratories; fabrication and BOM costs remain, and Panopto links need a manual access check.

Completion evidence

• Weekly learning log with time, questions, corrected errors, decisions, next steps, and links to that week's reproducible artifacts
• Design-review package with requirements and constraints, trade-offs, editable sources, applicable ERC/DRC/timing/stability checks, exports, and a reproduction test
• Code repository with pinned dependencies and toolchain, a minimal run command, tests or waveform/benchmark checks, expected output, and license notes
• Experiment package with schematic/setup, calibration record, raw data, uncertainty, safety checks, failed runs, and steps to rebuild plots from raw data