Microelectronics¶

Course Overview¶

• Institution: Cornell University
• Course code: ECE 3150
• Track: Microelectronics
• Tier: S
• Role: Mainline
• Level: Not standardized by provider (use prerequisites)
• Last reviewed: 2026-07-28

Cornell University's Microelectronics forms a text-first microelectronics spine from 27 notes, twelve solved homework sets, solved exams, and four labs, providing a complete feedback loop without videos.

Why choose this course

Mainline course. A particularly complete and well-structured option for this track.

Before you start

• Recommended foundation: Semiconductor Devices
• Recommended foundation: Circuit Analysis

Verifiable learning outcomes

• Explain the core models in Microelectronics, including their assumptions and limits
• Solve representative derivations and problems, checking units, limiting cases, or numerical results
• Complete a reproducible experiment or implementation with raw data, parameters, versions, and verification

Workload and pacing

13 weeks at 11 hours/week. This maintainer planning estimate is derived from course role and the density of public practice and labs; it is not a provider workload promise. Pilot two weeks while logging instruction, practice, lab, and review time, then adjust the remaining plan when actual effort differs by more than 25%.

Safety level

Low energy. Keep work isolated, current-limited, and low energy; verify ratings, grounding, short-circuit risk, and emergency shutdown before power-up.

Course Resources¶

Software, hardware, and cost

Software

• Maintainer-suggested open-source/free verification path: ngspice, Qucs-S, KiCad, Python 3, and Jupyter
• The resource inventory does not list public code coverage; the tools above are only a maintainer-suggested independent check, not a provider requirement

Hardware

• The resource inventory lists lab coverage; prefer borrowing or sharing the following equipment: course-specified devices, a current-limited low-voltage supply, breadboard or test PCB, digital multimeter, and oscilloscope. Verify ratings, authorization, and safety conditions only after the provider lab manual explicitly calls for them

Cost note

The suggested software stack is available open source or free; this is not a provider requirement or bill of materials. The actual boards, components, fabrication, and instruments—and their costs—depend on the provider lab manual, region, and local availability; prefer simulation, borrowing, or sharing before purchase.

Public resource coverage

Resources and access

“Listed by official page” means the link was discovered on a successfully fetched official source on the verification date; it does not guarantee that every region or account can open the target directly. Access does not grant redistribution rights. Re-check the provider page, target link, and third-party notices before downloading, adapting, or publishing material.

Practice and Verification¶

Practice loop

Microelectronics · Cornell University ECE 3150: Transistor-Level Amplifier Corner Validation

This is a maintainer-suggested self-study project for Microelectronics · Cornell University ECE 3150, not an official course assignment. Design a transistor-level gain stage or logic gate for Microelectronics and validate bias, small-signal, transient, and process-voltage-temperature corners.

Origin: Maintainer-suggested project

Deliverables

• Calculations for device sizes, bias, supply, load, ratings, and target specifications
• Transistor-level schematic or netlist and DC, AC, transient, noise, and corner tests
• Raw waveforms and specification table for nominal and at least eight PVT or load corners
• A report explaining transconductance, output resistance, swing, delay, and worst corner

Verification

• Keep nominal operating current within 10% of hand analysis and meet the primary predeclared specifications
• Cover cutoff, region boundary, minimum supply, maximum load, and temperature extremes
• Cross-check gain or poles with a small-signal equivalent circuit within 15%
• Perturb device size or threshold and record the first bias failure and specification degradation

Reproducibility

• Commit schematic or netlist, models, calculations, corner configurations, and plotting sources
• Pin licensed or open PDK or model version, simulator, temperature, supplies, and seeds
• Preserve raw waveforms, operating points, corner logs, and the generated report

Safety boundary: Simulation only — Use only lawfully obtained device models in simulation; do not perform wafer processing, high-voltage probing, or package decapsulation.

Risks, gaps, and boundaries

No videos and taught in 2016, but 27 notes, twelve solved homeworks, solved exams, and four labs form a complete spine.

Completion evidence

• Weekly learning log with time, questions, corrected errors, decisions, next steps, and links to that week's reproducible artifacts
• Design-review package with requirements and constraints, trade-offs, editable sources, applicable ERC/DRC/timing/stability checks, exports, and a reproduction test
• Simulation package with model or netlist, inputs, solver and version, parameter-sweep script, benchmark comparison, expected results, and one rerun command
• Experiment package with schematic/setup, calibration record, raw data, uncertainty, safety checks, failed runs, and steps to rebuild plots from raw data