Introductory Digital Systems Laboratory¶

Course Overview¶

• Institution: MIT
• Course code: 6.111
• Track: FPGA and System-on-Chip Design
• Tier: A
• Role: Mainline
• Level: Not standardized by provider (use prerequisites)
• Last reviewed: 2026-07-28

MIT's Introductory Digital Systems Laboratory develops FPGA-based digital implementation through Verilog labs and final projects, with strong notes and practice constrained by dated boards and EDA workflows.

Why choose this course

Mainline course. A reliable option that can serve as a main course or strong alternative.

Before you start

• Recommended foundation: Digital Logic and Computation Structures
• Recommended foundation: Computer Architecture

Verifiable learning outcomes

• Explain the core models in FPGA and System-on-Chip Design, including their assumptions and limits
• Solve representative derivations and problems, checking units, limiting cases, or numerical results
• Complete a reproducible experiment or implementation with raw data, parameters, versions, and verification

Workload and pacing

12 weeks at 10 hours/week. This maintainer planning estimate is derived from course role and the density of public practice and labs; it is not a provider workload promise. Pilot two weeks while logging instruction, practice, lab, and review time, then adjust the remaining plan when actual effort differs by more than 25%.

Safety level

Low energy. Keep work isolated, current-limited, and low energy; verify ratings, grounding, short-circuit risk, and emergency shutdown before power-up.

Course Resources¶

Software, hardware, and cost

Software

• Maintainer-suggested open-source/free verification path: Yosys, nextpnr, Verilator, and GTKWave; install a provider-specified vendor toolchain only when the target device requires it and verify its license
• The resource inventory lists public code coverage; pin interpreter, dependencies, toolchain, datasets, and PDK versions where applicable

Hardware

• The resource inventory lists lab coverage; prefer borrowing or sharing the following equipment: a course-supported FPGA development board, USB/JTAG programmer, and logic analyzer. Verify ratings, authorization, and safety conditions only after the provider lab manual explicitly calls for them

Cost note

The suggested software stack is available open source or free; this is not a provider requirement or bill of materials. The actual boards, components, fabrication, and instruments—and their costs—depend on the provider lab manual, region, and local availability; prefer simulation, borrowing, or sharing before purchase.

Public resource coverage

Resources and access

“Listed by official page” means the link was discovered on a successfully fetched official source on the verification date; it does not guarantee that every region or account can open the target directly. Access does not grant redistribution rights. Re-check the provider page, target link, and third-party notices before downloading, adapting, or publishing material.

Practice and Verification¶

Practice loop

Introductory Digital Systems Laboratory · MIT 6.111: Synthesizable Streaming SoC Subsystem

This is a maintainer-suggested self-study project for Introductory Digital Systems Laboratory · MIT 6.111, not an official course assignment. Implement a synthesizable subsystem for FPGA and System-on-Chip Design with register, DMA or streaming, and interrupt interfaces; close simulation and timing before an optional low-voltage development-board demo.

Origin: Maintainer-suggested project

Deliverables

• A specification for registers, bus or stream interfaces, clocks, resets, and performance targets
• RTL, driver or firmware, reference model, assertions, and randomized testbench source files
• Logs, waveforms, coverage, utilization, and timing reports for at least 10,000 transactions
• A hardware-software co-design report covering throughput, latency, CDC risk, and one corrected defect

Verification

• Match the reference model bit-for-bit in randomized regression with zero unwaived protocol or CDC errors
• Cover transactions during reset, maximum bursts, sustained backpressure, counter wrap, and illegal register access
• Meet the predeclared post-synthesis clock constraint with worst slack at or above 0 ns
• Inject an interrupt-loss or clock-domain-crossing defect and show that assertions or tests catch it reliably

Reproducibility

• Commit RTL, firmware, constraints, tests, optional board pin files, and a README
• Pin simulation, synthesis, and SDK versions, device part, seeds, and a one-command regression
• Preserve raw regression, synthesis, timing, and optional board-console logs

Safety boundary: Low energy — Limit board demos to compliant low-voltage development boards with current-limited USB power; verify I/O ratings, levels, and pins and wire with power removed. No mains, high-current loads, or mechanisms.

Risks, gaps, and boundaries

The Verilog laboratories and final projects are strong, but the FPGA boards and EDA workflow are dated.

Completion evidence

• Weekly learning log with time, questions, corrected errors, decisions, next steps, and links to that week's reproducible artifacts
• Design-review package with requirements and constraints, trade-offs, editable sources, applicable ERC/DRC/timing/stability checks, exports, and a reproduction test
• Code repository with pinned dependencies and toolchain, a minimal run command, tests or waveform/benchmark checks, expected output, and license notes
• Simulation package with model or netlist, inputs, solver and version, parameter-sweep script, benchmark comparison, expected results, and one rerun command
• Experiment package with schematic/setup, calibration record, raw data, uncertainty, safety checks, failed runs, and steps to rebuild plots from raw data