Basic Overview of Semiconductor Device Processing and IC Fabrication¶

Course Overview¶

• Institution: IIT Kanpur / NPTEL
• Course code: 108104865
• Track: Micro/Nanofabrication and MEMS
• Tier: A
• Role: Supplement
• Level: Not standardized by provider (use prerequisites)
• Last reviewed: 2026-07-28

IIT Kanpur / NPTEL's Basic Overview of Semiconductor Device Processing and IC Fabrication offers a current 2026 overview through a strong lecture spine, while lacking labs, code, and open grading feedback.

Why choose this course

Supplement course. A reliable option that can serve as a main course or strong alternative. Review note: A-

Before you start

• Recommended foundation: Semiconductor Devices
• Recommended foundation: Physics Foundations

Verifiable learning outcomes

• Explain the core models in Micro/Nanofabrication and MEMS, including their assumptions and limits
• Solve representative derivations and problems, checking units, limiting cases, or numerical results

Workload and pacing

5 weeks at 4 hours/week. This maintainer planning estimate is derived from course role and the density of public practice and labs; it is not a provider workload promise. Pilot two weeks while logging instruction, practice, lab, and review time, then adjust the remaining plan when actual effort differs by more than 25%.

Safety level

Standard study. No physical lab is recorded; follow ordinary electrical, ergonomic, data, and equipment-use precautions.

Course Resources¶

Software, hardware, and cost

Software

• Maintainer-suggested open-source/free verification path: KLayout, gdsfactory, Python 3, and Jupyter
• The resource inventory does not list public code coverage; the tools above are only a maintainer-suggested independent check, not a provider requirement

Hardware

• The resource inventory does not list public lab coverage; default to simulation and do not purchase institution-approved cleanroom, process tools, metrology, and personal protective equipment; do not substitute home purchases. If extending the course independently, first verify provider scope and reassess safety

Cost note

The current maintainer path assumes no dedicated hardware purchase and prefers open-source/free software; this is not a provider requirement. If the provider separately lists commercial software, components, equipment, or institutional access, costs vary by provider, region, and institution.

Public resource coverage

Resources and access

“Listed by official page” means the link was discovered on a successfully fetched official source on the verification date; it does not guarantee that every region or account can open the target directly. Access does not grant redistribution rights. Re-check the provider page, target link, and third-party notices before downloading, adapting, or publishing material.

Practice and Verification¶

Practice loop

Basic Overview of Semiconductor Device Processing and IC Fabrication · IIT Kanpur / NPTEL 108104865: MEMS Process-Flow and Tolerance Digital Validation

This is a maintainer-suggested self-study project for Basic Overview of Semiconductor Device Processing and IC Fabrication · IIT Kanpur / NPTEL 108104865, not an official course assignment. Propose a virtual MEMS or microfabricated structure and process flow for Micro/Nanofabrication and MEMS, then simulate geometry, residual stress, etch bias, and failure margin.

Origin: Maintainer-suggested project

Deliverables

• Device cross section, mask layers, materials, process sequence, design rules, and risk analysis
• Parameterized geometry or finite-element model and process-tolerance sweep sources
• Raw displacement, frequency, stress, thermal or fluid results and at least 100 tolerance samples
• A report defining process window, yield proxy, failure modes, and layout correction

Verification

• Keep the nominal key response within 10% of a simplified beam or membrane analytic model
• Cover minimum feature, maximum etch bias, material extremes, and contact or buckling boundaries
• After mesh refinement, keep the key metric change below 5% and report energy or force balance
• Inject residual stress or mask misalignment and locate the first design-rule or performance failure

Reproducibility

• Commit cross-section or mask, parametric geometry, solver, sweep, and post-processing sources
• Pin solver, material library, meshing rules, process parameters, and tolerance seeds
• Preserve raw field and geometry data, solver logs, and the generated report

Safety boundary: Simulation only — Use process planning and simulation only; do not use chemicals, vacuum, plasma, lithography, cleanroom equipment, or physical micromechanical structures.

Risks, gaps, and boundaries

The 2026 archive provides a strong lecture spine but no reproducible laboratory, code, or open grading feedback.

Completion evidence

• Weekly learning log with time, questions, corrected errors, decisions, next steps, and links to that week's reproducible artifacts
• Design-review package with requirements and constraints, trade-offs, editable sources, applicable ERC/DRC/timing/stability checks, exports, and a reproduction test