Circuits and Electronics¶

Course Overview¶

• Institution: MIT
• Course code: 6.002
• Track: Circuit Analysis
• Tier: S
• Role: Mainline
• Level: Not standardized by provider (use prerequisites)
• Last reviewed: 2026-07-28

MIT's Circuits and Electronics provides a mainline course in circuit analysis and electronics, with unusually complete videos, notes, problems, labs, and exams connecting derivation to measurement.

Why choose this course

Mainline course. A particularly complete and well-structured option for this track.

Before you start

• Recommended foundation: Engineering Mathematics
• Recommended foundation: Physics Foundations

Verifiable learning outcomes

• Explain the core models in Circuit Analysis, including their assumptions and limits
• Solve representative derivations and problems, checking units, limiting cases, or numerical results
• Complete a reproducible experiment or implementation with raw data, parameters, versions, and verification

Workload and pacing

13 weeks at 11 hours/week. This maintainer planning estimate is derived from course role and the density of public practice and labs; it is not a provider workload promise. Pilot two weeks while logging instruction, practice, lab, and review time, then adjust the remaining plan when actual effort differs by more than 25%.

Safety level

Low energy. Keep work isolated, current-limited, and low energy; verify ratings, grounding, short-circuit risk, and emergency shutdown before power-up.

Course Resources¶

Software, hardware, and cost

Software

• Maintainer-suggested open-source/free verification path: Qucs-S, ngspice, Python 3, and Jupyter
• The resource inventory lists public code coverage; pin interpreter, dependencies, toolchain, datasets, and PDK versions where applicable

Hardware

• The resource inventory lists lab coverage; prefer borrowing or sharing the following equipment: a current-limited low-voltage supply, breadboard, digital multimeter, oscilloscope, and function generator. Verify ratings, authorization, and safety conditions only after the provider lab manual explicitly calls for them

Cost note

The suggested software stack is available open source or free; this is not a provider requirement or bill of materials. The actual boards, components, fabrication, and instruments—and their costs—depend on the provider lab manual, region, and local availability; prefer simulation, borrowing, or sharing before purchase.

Public resource coverage

Resources and access

“Listed by official page” means the link was discovered on a successfully fetched official source on the verification date; it does not guarantee that every region or account can open the target directly. Access does not grant redistribution rights. Re-check the provider page, target link, and third-party notices before downloading, adapting, or publishing material.

Practice and Verification¶

Practice loop

Circuits and Electronics · MIT 6.002: Dynamic Network Model and Tolerance Validation

This is a maintainer-suggested self-study project for Circuits and Electronics · MIT 6.002, not an official course assignment. Design a low-voltage resistive, capacitive, and optionally op-amp network for Circuit Analysis; compare hand analysis, SPICE, and current-limited measurements while studying tolerance and saturation failures.

Origin: Maintainer-suggested project

Deliverables

• A schematic and analytic calculation with named nodes, ratings, supplies, and test points
• An executable SPICE netlist containing DC, AC, transient, and Monte Carlo analyses
• Raw simulation data at at least 20 frequencies or time points and optional low-voltage measurement data
• A report comparing the three evidence paths and explaining tolerance, noise, loading, and saturation

Verification

• Keep nominal DC node voltages within 2% of hand analysis and AC cutoff frequency within 5%
• Check open-circuit, short-circuit, zero-frequency, and high-frequency limits against equivalent-circuit expectations
• Cross-check every operating point with KCL or KVL residual below 1e-6 after normalization
• Inject ±10% component tolerance and one output-saturation case and report the worst metric and recovery condition

Reproducibility

• Commit schematics, netlists, calculation sources, data-analysis scripts, and a README
• Pin SPICE version, model files, analysis parameters, and optional instrument settings
• Preserve unprocessed waveforms, export logs, photos or wiring diagrams, and the generated report

Safety boundary: Low energy — Use only isolated, current-limited circuits at or below 12 V; verify power ratings and polarity, wire with power removed, and never use mains or unknown supplies.

Risks, gaps, and boundaries

The tools and component references are dated, but the teaching and assessment spine is exceptionally complete.

Completion evidence

• Weekly learning log with time, questions, corrected errors, decisions, next steps, and links to that week's reproducible artifacts
• Theory dossier with explicit assumptions, notation, derivation, units, and boundary conditions, checked by at least one independent method
• Simulation package with model or netlist, inputs, solver and version, parameter-sweep script, benchmark comparison, expected results, and one rerun command
• Code repository with pinned dependencies and toolchain, a minimal run command, tests or waveform/benchmark checks, expected output, and license notes
• Experiment package with schematic/setup, calibration record, raw data, uncertainty, safety checks, failed runs, and steps to rebuild plots from raw data