Analog IC Design¶

Course Overview¶

• Institution: IIT Madras / NPTEL
• Course code: 108106105 / NOC26-EE66
• Track: Analog and Mixed-Signal IC Design
• Tier: A
• Role: Mainline
• Level: Advanced
• Last reviewed: 2026-07-28

IIT Madras / NPTEL's Analog IC Design provides a current 2026 twelve-week video spine for analog integrated-circuit design with the 2018 archive retained as a supplement, while graded feedback and the certificate exam depend on enrollment and no open EDA project is provided.

Why choose this course

Mainline course. A reliable option that can serve as a main course or strong alternative. Review note: A content / B completion

Before you start

• Recommended foundation: Microelectronics
• Recommended foundation: Analog Electronics

Verifiable learning outcomes

• Explain the core models in Analog and Mixed-Signal IC Design, including their assumptions and limits
• Solve representative derivations and problems, checking units, limiting cases, or numerical results

Workload and pacing

12 weeks at 8 hours/week. The provider publishes 12 weeks; the weekly effort above is a maintainer planning estimate derived from course role and public practice/lab density, not a provider promise. Pilot two weeks and adjust when actual effort differs by more than 25%.

Safety level

Simulation only. The default practice scope is software, computation, or simulation only; a lab label in the resource inventory does not authorize connecting physical equipment, and any hardware extension requires provider-scope verification and a new risk assessment.

Course Resources¶

Software, hardware, and cost

Software

• Maintainer-suggested open-source/free verification path: xschem, ngspice, KLayout, Magic, and an open PDK explicitly supported by the tutorial
• The resource inventory does not list public code coverage; the tools above are only a maintainer-suggested independent check, not a provider requirement

Hardware

• The resource inventory does not list public physical-lab coverage; the maintainer path defaults to computation/simulation. It assumes only a computer that can run the PDK, corner simulations, and layout checks; no tape-out or physical chip is assumed. If the provider lists different equipment or compute requirements, follow its course page

Cost note

The suggested software stack is available open source or free; this is maintainer planning, not a provider requirement. If the provider specifies commercial licenses, cloud compute, storage, or institutional resources, costs vary by plan, region, and institution, so no fixed price is asserted here.

Public resource coverage

Resources and access

“Listed by official page” means the link was discovered on a successfully fetched official source on the verification date; it does not guarantee that every region or account can open the target directly. Access does not grant redistribution rights. Re-check the provider page, target link, and third-party notices before downloading, adapting, or publishing material.

Practice and Verification¶

Practice loop

Analog IC Design · IIT Madras / NPTEL 108106105 / NOC26-EE66: Op-Amp or Data-Converter Specification Closure

This is a maintainer-suggested self-study project for Analog IC Design · IIT Madras / NPTEL 108106105 / NOC26-EE66, not an official course assignment. Close transistor-level specifications for an op-amp or compact data converter in Analog and Mixed-Signal IC Design, covering stability, noise, linearity, PVT, and mismatch Monte Carlo.

Origin: Maintainer-suggested project

Deliverables

• A specification and testbench matrix covering load, common mode, output swing, power, and noise
• Transistor-level design, bias network, every testbench, and automated metric-extraction scripts
• Raw waveforms and metrics for nominal, PVT, and at least 200 mismatch Monte Carlo runs
• A report giving specification yield, Pareto tradeoffs, worst sample, and corrective change

Verification

• Pass every primary nominal specification and keep hand-estimated versus simulated open or closed-loop gain within 15%
• Cover common-mode and output-swing limits, maximum capacitive load, minimum supply, and temperature extremes
• Cross-check input-referred noise or linearity through a second noise-integration or FFT method
• Meet the predeclared Monte Carlo yield and reproduce and explain the worst failing sample

Reproducibility

• Commit design, bias, testbench, metric-extraction, and report sources
• Pin PDK or models, simulator, corners, Monte Carlo seeds, and tolerances
• Preserve all raw waveforms and metrics, failing-sample configurations, and the generated report

Safety boundary: Simulation only — Use transistor-level simulation only and honor PDK or model licenses; no tape-out, probe-station, high-voltage, or unauthorized commercial-EDA activity.

Risks, gaps, and boundaries

The current 2026 run provides a structured 12-week video syllabus, but graded feedback and the optional certificate exam depend on enrollment, and no open EDA project is provided.

Completion evidence

• Weekly learning log with time, questions, corrected errors, decisions, next steps, and links to that week's reproducible artifacts
• Design-review package with requirements and constraints, trade-offs, editable sources, applicable ERC/DRC/timing/stability checks, exports, and a reproduction test
• Simulation package with model or netlist, inputs, solver and version, parameter-sweep script, benchmark comparison, expected results, and one rerun command