Analog Circuits¶

Course Overview¶

• Institution: IIT Bombay / NPTEL
• Course code: 108101094
• Track: Analog Electronics
• Tier: A
• Role: Alternative
• Level: Not standardized by provider (use prerequisites)
• Last reviewed: 2026-07-28

IIT Bombay / NPTEL's Analog Circuits provides a current analog-circuit lecture sequence through 2026 videos and weekly assignments, but lacks labs, code, and public solution feedback.

Why choose this course

Alternative course. A reliable option that can serve as a main course or strong alternative.

Before you start

• Recommended foundation: Circuit Analysis
• Recommended foundation: Electronics Laboratory and Measurement

Verifiable learning outcomes

• Explain the core models in Analog Electronics, including their assumptions and limits
• Solve representative derivations and problems, checking units, limiting cases, or numerical results

Workload and pacing

8 weeks at 6 hours/week. This maintainer planning estimate is derived from course role and the density of public practice and labs; it is not a provider workload promise. Pilot two weeks while logging instruction, practice, lab, and review time, then adjust the remaining plan when actual effort differs by more than 25%.

Safety level

Standard study. No physical lab is recorded; follow ordinary electrical, ergonomic, data, and equipment-use precautions.

Course Resources¶

Software, hardware, and cost

Software

• Maintainer-suggested open-source/free verification path: Qucs-S, ngspice, KiCad, Python 3, and Jupyter
• The resource inventory does not list public code coverage; the tools above are only a maintainer-suggested independent check, not a provider requirement

Hardware

• The resource inventory does not list public lab coverage; default to simulation and do not purchase a current-limited low-voltage supply, breadboard, digital multimeter, oscilloscope, function generator, and course-specified devices. If extending the course independently, first verify provider scope and reassess safety

Cost note

The current maintainer path assumes no dedicated hardware purchase and prefers open-source/free software; this is not a provider requirement. If the provider separately lists commercial software, components, equipment, or institutional access, costs vary by provider, region, and institution.

Public resource coverage

Resources and access

“Listed by official page” means the link was discovered on a successfully fetched official source on the verification date; it does not guarantee that every region or account can open the target directly. Access does not grant redistribution rights. Re-check the provider page, target link, and third-party notices before downloading, adapting, or publishing material.

Practice and Verification¶

Practice loop

Analog Circuits · IIT Bombay / NPTEL 108101094: Analog Front-End Gain–Noise–Distortion Trade Study

This is a maintainer-suggested self-study project for Analog Circuits · IIT Bombay / NPTEL 108101094, not an official course assignment. Design a low-voltage analog front end for Analog Electronics and quantify gain, bandwidth, noise, distortion, and saturation tradeoffs in SPICE with an optional current-limited prototype.

Origin: Maintainer-suggested project

Deliverables

• A schematic and small-signal analysis covering bias, device ratings, stability, and test points
• A SPICE project with operating-point, AC, noise, transient, and tolerance sweeps
• Raw frequency response, output noise, THD, and clipping waveforms at at least three input amplitudes
• A design report containing a specification matrix, tradeoffs, worst corner, and corrected failure

Verification

• Keep nominal midband gain within 5% of design and meet the predeclared −3 dB bandwidth
• Verify minimum input, maximum linear input, common-mode boundary, and supply-headroom cases
• Cross-check hand-calculated transconductance, gain, and poles against SPICE within 10%
• Double the load or apply a device corner and report the first phase-margin, THD, or output-swing failure

Reproducibility

• Commit schematics, models, netlists, calculations, plotting sources, and a README
• Pin simulator and device-model versions, tolerance seeds, and all analysis parameters
• Preserve unprocessed waveforms, measurement settings, and the automatically generated specification report

Safety boundary: Low energy — Limit physical prototypes to isolated, current-limited supplies at or below 12 V; verify power ratings and polarity and wire with power removed. No mains, human connection, or high-power loads.

Risks, gaps, and boundaries

Current 2026 videos and weekly assignments, but no laboratory, code, or public solution feedback.

Completion evidence

• Weekly learning log with time, questions, corrected errors, decisions, next steps, and links to that week's reproducible artifacts
• Design-review package with requirements and constraints, trade-offs, editable sources, applicable ERC/DRC/timing/stability checks, exports, and a reproduction test
• Simulation package with model or netlist, inputs, solver and version, parameter-sweep script, benchmark comparison, expected results, and one rerun command