Solid-State Circuits¶

Course Overview¶

• Institution: MIT
• Course code: 6.301
• Track: Analog Electronics
• Tier: B
• Role: Supplement
• Level: Not standardized by provider (use prerequisites)
• Last reviewed: 2026-07-28

MIT's Solid-State Circuits supplements solid-state analog circuit training with problems, labs, and exams, but missing classroom notes make 6.012-equivalent preparation and outside reading essential.

Why choose this course

Supplement course. Useful for specific topics and best paired with a more complete mainline resource.

Before you start

• Recommended foundation: Circuit Analysis
• Recommended foundation: Electronics Laboratory and Measurement

Verifiable learning outcomes

• Explain the core models in Analog Electronics, including their assumptions and limits
• Solve representative derivations and problems, checking units, limiting cases, or numerical results
• Complete a reproducible experiment or implementation with raw data, parameters, versions, and verification

Workload and pacing

7 weeks at 6 hours/week. This maintainer planning estimate is derived from course role and the density of public practice and labs; it is not a provider workload promise. Pilot two weeks while logging instruction, practice, lab, and review time, then adjust the remaining plan when actual effort differs by more than 25%.

Safety level

Low energy. Keep work isolated, current-limited, and low energy; verify ratings, grounding, short-circuit risk, and emergency shutdown before power-up.

Course Resources¶

Software, hardware, and cost

Software

• Maintainer-suggested open-source/free verification path: Qucs-S, ngspice, KiCad, Python 3, and Jupyter
• The resource inventory does not list public code coverage; the tools above are only a maintainer-suggested independent check, not a provider requirement

Hardware

• The resource inventory lists lab coverage; prefer borrowing or sharing the following equipment: a current-limited low-voltage supply, breadboard, digital multimeter, oscilloscope, function generator, and course-specified devices. Verify ratings, authorization, and safety conditions only after the provider lab manual explicitly calls for them

Cost note

The suggested software stack is available open source or free; this is not a provider requirement or bill of materials. The actual boards, components, fabrication, and instruments—and their costs—depend on the provider lab manual, region, and local availability; prefer simulation, borrowing, or sharing before purchase.

Public resource coverage

Resources and access

“Listed by official page” means the link was discovered on a successfully fetched official source on the verification date; it does not guarantee that every region or account can open the target directly. Access does not grant redistribution rights. Re-check the provider page, target link, and third-party notices before downloading, adapting, or publishing material.

Practice and Verification¶

Practice loop

Solid-State Circuits · MIT 6.301: Analog Front-End Gain–Noise–Distortion Trade Study

This is a maintainer-suggested self-study project for Solid-State Circuits · MIT 6.301, not an official course assignment. Design a low-voltage analog front end for Analog Electronics and quantify gain, bandwidth, noise, distortion, and saturation tradeoffs in SPICE with an optional current-limited prototype.

Origin: Maintainer-suggested project

Deliverables

• A schematic and small-signal analysis covering bias, device ratings, stability, and test points
• A SPICE project with operating-point, AC, noise, transient, and tolerance sweeps
• Raw frequency response, output noise, THD, and clipping waveforms at at least three input amplitudes
• A design report containing a specification matrix, tradeoffs, worst corner, and corrected failure

Verification

• Keep nominal midband gain within 5% of design and meet the predeclared −3 dB bandwidth
• Verify minimum input, maximum linear input, common-mode boundary, and supply-headroom cases
• Cross-check hand-calculated transconductance, gain, and poles against SPICE within 10%
• Double the load or apply a device corner and report the first phase-margin, THD, or output-swing failure

Reproducibility

• Commit schematics, models, netlists, calculations, plotting sources, and a README
• Pin simulator and device-model versions, tolerance seeds, and all analysis parameters
• Preserve unprocessed waveforms, measurement settings, and the automatically generated specification report

Safety boundary: Low energy — Limit physical prototypes to isolated, current-limited supplies at or below 12 V; verify power ratings and polarity and wire with power removed. No mains, human connection, or high-power loads.

Risks, gaps, and boundaries

The primary classroom notes are missing; the course depends on 6.012-equivalent preparation and outside readings.

Completion evidence

• Weekly learning log with time, questions, corrected errors, decisions, next steps, and links to that week's reproducible artifacts
• Design-review package with requirements and constraints, trade-offs, editable sources, applicable ERC/DRC/timing/stability checks, exports, and a reproduction test
• Simulation package with model or netlist, inputs, solver and version, parameter-sweep script, benchmark comparison, expected results, and one rerun command
• Experiment package with schematic/setup, calibration record, raw data, uncertainty, safety checks, failed runs, and steps to rebuild plots from raw data